In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The minimum dimension or feature size (F) of the features and spaces depends on the resolution capability of the lithographic systems. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC).
In advanced IC designs, different devices have different requirements to produce device features of different sizes. As a result, the device layer has features and spaces of varying sizes, creating a complex topography. A dielectric material, such as oxide, is used to fill the spaces between the features. Such material is typically deposited by various known chemical vapor deposition techniques. The deposited oxide material forms a conformal layer over the underlying device layer. As such, the deposited oxide material comprises a topography that reflects the topography of the underlying layer, reproducing the non-planar surface. The non-planar surface is then planarized by, for example, chemical mechanical polish to produce a planar surface. A planar surface is desired as it allows the formation of additional device layers to create additional device structures thereover, thus increasing device density.
As the size of features decrease in advance IC designs, the spaces between the features become smaller which results in features with a high aspect ratio. Small high aspect ratio features make it difficult to fill the spaces with conventional CVD techniques. To facilitate gap fill of smaller spaces, high density plasma (HDP) CVD of oxide has been used.
HDP-CVD oxide creates a non-conformal layer. The non-conformal layer has a non-planar surface that does not reflect the topography of the underlying layer. The thickness of the non-conformal is greater above wide device features and thinner above the narrower device features. Such a topography creates difficulties for conventional planarization schemes to produce a planar surface. In particular, excessive erosion of the narrower device features occurs because there exists a greater amount of deposited material over the wider device features than the narrower device features. Such excessive erosion adversely impacts the operation or functionality of the narrower devices, thereby decreasing yield.
The above discussion makes evident that is desirable to achieve a planar surface after deposition of a non-conformal layer without excessive erosion of some device features.